NVIDIA GPU Families: RTX vs. A, H, B and Rubin
How the consumer and pro RTX cards differ from the data-center A, H, B and Rubin parts and the Grace superchips. Which ones are built for HPC and why. And what NVIDIA is betting on for training versus inference, read from its own spec sheets.
Part 1
The map: four product lines
The letters matter less than which line a part belongs to. Each line makes different choices about memory, interconnect, FP64, isolation and licensing.
| Line | Parts | Memory | Built for |
|---|---|---|---|
| GeForce RTX | RTX 5090 | GDDR7 | Gaming and creators. The driver licence says it "is not licensed for datacenter deployment." NVIDIA |
| Pro / data-center PCIe (Ada "L", RTX PRO) | L4, L40S, RTX PRO 6000 Blackwell Server Edition | GDDR6/7 with ECC | Inference, graphics, video and virtual desktops in ordinary air-cooled PCIe servers |
| Data-center SXM (A → H → B → Rubin) | A100, H100, H200, B200, B300, Rubin | HBM | Training, large-scale inference and HPC: NVLink domains, MIG, FP64 (with one exception, Part 5) |
| Superchips and rack scale | GH200, GB200, GB300 NVL72, Vera Rubin NVL72; DGX Spark (GB10) at desk scale | HBM plus coherent CPU LPDDR5X | A Grace or Vera CPU fused to GPUs over NVLink-C2C; whole racks as one NVLink domain |
Generations, oldest first: Ampere (A100, 2020) → Ada (L4, L40S) and Hopper (H100, H200, GH200) → Blackwell (B200, GB200, RTX 50, RTX PRO) → Blackwell Ultra (B300, GB300) → Rubin (Vera Rubin, ramping now) → Rubin Ultra (roadmap, H2 2027).
Part 2
Every part, one table
Per GPU unless noted. FP8 and FP4 as NVIDIA lists them (sparse) unless marked dense. A dash means NVIDIA doesn't list it.
| Part | Memory · bandwidth | FP64 native | FP8 / FP4 | Interconnect | MIG | Video encode | Power · form | Status |
|---|---|---|---|---|---|---|---|---|
| A100 SXM | 80 GB HBM2e · 2.0 TB/s | 9.7 TF (19.5 tensor) | none | NVLink 3 · 600 GB/s | 7 | unverified | 400 W · SXM | shipping since 2020 |
| H100 SXM | 80 GB HBM3 · 3.35 TB/s | 34 TF (67 tensor) | FP8 3.96 PF; no FP4 | NVLink 4 · 900 GB/s | 7 | No NVENC (7 NVDEC) | 700 W · SXM | shipping |
| H200 SXM | 141 GB HBM3e · 4.8 TB/s | 34 TF (67 tensor) | FP8 3.96 PF | NVLink 4 · 900 GB/s | 7 | No NVENC (7 NVDEC) | 700 W · SXM | shipping |
| B200 | 180–192 GB HBM3e · 8 TB/s | ~37 TF | FP8 5 PF dense; FP4 10 PF dense | NVLink 5 · 1.8 TB/s | count unverified | decoders listed | up to 1,200 W · SXM | shipping |
| B300 (Blackwell Ultra) | 288 GB HBM3e · 8 TB/s | ~1.25 TF | FP8 5 PF dense; FP4 15 PF dense | NVLink 5 · 1.8 TB/s | yes | decoders listed | up to 1,400 W · SXM | shipping |
| Rubin (Vera Rubin) | 288 GB HBM4 · 19.2 TB/s | 33 TF (200 "matrix" via emulation) | NVFP4 50 PF inference / 35 PF training | NVLink 6 · 3 TB/s | unverified | unverified | unverified | ramping; racks running at partners (Aug 2026) |
| Rubin CPX | 128 GB GDDR7 | — | NVFP4 30 PF | — | — | has encoders | — | announced Sep 2025 for end of 2026; status disputed (Part 6) |
| L4 | 24 GB GDDR6 · 300 GB/s | — | FP8 485 TF | PCIe Gen4 only | — | 2 NVENC · 4 NVDEC | 72 W · 1-slot low-profile | shipping |
| L40S | 48 GB GDDR6 ECC · 864 GB/s | — | FP8 1.47 PF | PCIe Gen4, NVLink "No" | "No" | 3 NVENC · 3 NVDEC | 350 W · dual-slot | shipping; vGPU yes |
| RTX PRO 6000 Blackwell Server | 96 GB GDDR7 ECC · 1.6 TB/s | — (low; see Part 5) | FP8 2 PF; FP4 4 PF | PCIe Gen5, no NVLink | up to 4 | 9th-gen NVENC | 600 W · dual-slot | shipping |
| GeForce RTX 5090 | 32 GB GDDR7 | — | 3,352 "AI TOPS" (FP4, sparse) | no NVLink | no | 3 NVENC · 2 NVDEC | 575 W | shipping; not licensed for data centers |
Superchips and racks
| System | What's in it | Memory | FP64 | Low-precision | Status |
|---|---|---|---|---|---|
| GH200 | 1 Grace + 1 Hopper, NVLink-C2C 900 GB/s | 96–144 GB HBM + up to 480 GB LPDDR5X | 34 TF (67 tensor) | as H100 | shipping |
| GB200 NVL72 | 36 Grace + 72 B200 in one NVLink domain (130 TB/s) | 13.4 TB HBM3e · 576 TB/s | rack 2,880 TF | FP4 720 PF dense | shipping |
| GB300 NVL72 | 36 Grace + 72 Blackwell Ultra | 20 TB HBM3e + 17 TB LPDDR5X | rack 100 TF | FP4 1,080 PF dense | available now |
| Vera Rubin NVL72 (once called NVL144) | Vera CPUs + 72 Rubin packages (144 dies), NVLink 6, rack 216 TB/s; C2C 1.8 TB/s | HBM4; Vera up to 1.5 TB LPDDR5X | rack 2,400 TF (72 × 33) | NVFP4 50 PF per GPU | ramping (Aug 2026) |
| DGX Spark (GB10) | Grace Blackwell on a desk; ConnectX-7 200 Gb/s | 128 GB unified LPDDR5x · 273 GB/s | — | "up to 1 PF FP4" (sparse) | shipping |
Rubin racks were "NVL144" at GTC 2025 (counting dies) and "NVL72" by January 2026 (counting packages). Same rack. NVIDIA's own pages also disagree in places: the GB200 NVL72 page lists INT8 at 720 POPS where HGX B200 lists 72, and GB300 FP64 works out to ~1.39 TF per GPU on one page and ~1.25 on another. Always ask "dense or sparse, per GPU or per rack, dies or packages" before a number goes into a comparison. NVIDIA pages, footer
Rubin's figures moved between the January 2026 blog and the product page: memory bandwidth "up to 22 TB/s" became 19.2 TB/s, NVLink "3.6 TB/s" per GPU became 3 TB/s, and the rack's "260 TB/s" became 216 TB/s. This page carries the product page's figures. Power for B200 and B300 is NVIDIA's "Up to" maximum from Table 2 of the Blackwell Ultra blog; the HGX page no longer lists power. NVIDIA A deployed configuration can sit below the maximum, so a planning figure under it is not by itself wrong, but it should say which configuration it is. reasoned
Part 3
RTX vs. data center: what actually differs
The same architecture name, e.g. Blackwell, covers both an RTX 5090 and a B200. The silicon and the product choices around it are very different.
| Property | RTX / L / RTX PRO | A / H / B / Rubin (SXM) | Why it matters |
|---|---|---|---|
| Memory | GDDR6/GDDR7, 24–96 GB, 0.3–1.8 TB/s | HBM, 80–288 GB, 2–19.2 TB/s | Decode speed is bounded by memory bandwidth, so HBM parts generate tokens far faster per GPU |
| GPU-to-GPU | PCIe only; no NVLink on L4, L40S, RTX PRO 6000 or RTX 5090 | NVLink 600 GB/s → 3 TB/s per GPU; whole-rack domains from GB200 on | Tensor-parallel training and big-model serving need NVLink. PCIe cards are single-GPU or loosely coupled |
| FP64 | Not listed; a small fraction of FP32 exact ratio unverified | 9.7–37 TF native (except B300, Part 5) | Simulation codes (CFD, weather, chemistry) need FP64 |
| ECC | Stated on L40S and RTX PRO; GeForce consumer parts not | Yes | Silent bit flips matter on week-long jobs and in billing disputes |
| Isolation | MIG: L40S no, RTX PRO 6000 up to 4; vGPU on L40S | MIG up to 7 | Hard multi-tenancy via containers, MIG and a DPU |
| Video | NVENC + NVDEC (L4: 2 + 4; L40S: 3 + 3) | H100/H200: decoders only, no NVENC | Transcoding and video AI belong on L4-class cards. It's why the codec experiment can't run on H100 |
| Power and cooling | 72–600 W, air-cooled PCIe, fits standard servers | 400 W to as much as 1,400 W per GPU (NVIDIA's stated maxima); GB/VR racks are liquid-cooled | A facility that can't do liquid cooling is limited to PCIe parts and HGX air configurations |
| Licence | GeForce: "not licensed for datacenter deployment" | Data-center drivers and NVIDIA AI Enterprise | A GeForce-based cloud offering is a licensing problem, not just a technical one |
RTX and L-class parts are compute in a standard server. A/H/B/Rubin parts are compute plus HBM bandwidth, NVLink, FP64 and MIG, and those four are what you pay for. If a workload needs none of them (single-GPU inference of a model that fits in 48–96 GB, video, graphics), the PCIe card is the efficient choice. reasoned
Part 4
Superchips: what Grace buys
A "superchip" is an NVIDIA Arm CPU (Grace, now Vera) joined to one or two GPUs by NVLink-C2C, a coherent link instead of PCIe. NVIDIA: 900 GB/s, "7X faster than PCIe Gen5," and "the CPU and GPU share a single per-process page table, enabling all CPU and GPU threads to access all system-allocated memory." NVIDIA GH200 page Vera Rubin doubles C2C to 1.8 TB/s, with up to 1.5 TB of CPU memory.
- What it buys: the GPU can use hundreds of GB of CPU LPDDR5X as a slower, coherent extension of HBM. That helps with KV-cache spill, giant embedding tables, graph and HPC codes whose data doesn't fit in HBM, and offloading optimizer state.
- What it costs: you're on Arm (aarch64) for the host, and you buy the CPU NVIDIA chose. Most x86-only software and agents need rebuilding or validation.
- Superchip vs. rack: GB200 and GB300 are sold mainly as NVL72 racks: 72 GPUs in one NVLink domain (130 TB/s). The rack, not the chip, is the unit of purchase, power and cooling. reasoned
- Desk scale: DGX Spark (GB10) puts the same idea in a 150 mm box, with 128 GB of unified memory, enough for local development against the same software stack.
Part 5
HPC and FP64: the quiet split
For a decade every flagship NVIDIA data-center GPU was an HPC part too. Blackwell Ultra broke that, and Rubin partly restores it.
| Part | Native FP64 per GPU | What happened |
|---|---|---|
| A100 | 9.7 TF (19.5 via tensor cores) | FP64 tensor cores arrive |
| H100 / H200 | 34 TF (67 tensor) | The HPC peak of the line |
| B200 | ~37 TF | HGX B200 lists 296 TF for 8 GPUs |
| B300 | ~1.25 TF | HGX B300 lists "FP64/FP64 Tensor Core 10 TFLOPS" for 8 GPUs, against B200's 296. INT8 falls from 72 to 3 POPS. The area went to FP4. NVIDIA's Blackwell Ultra blog leaves FP64 out of its comparison table. |
| Rubin | 33 TF (200 "matrix" via emulation) | Native FP64 back near Hopper level. The NVL72 product page lists 2,400 TF per rack, which is 72 × 33. The ISC release (June 2026) says "5 petaflops of native FP64" and "performance on par with systems on the TOP500 list" for a system "with up to 144 GPUs", under a headline that says a single rack. 144 × 33 TF is 4.75 PF, so the two agree per GPU and differ on how many GPUs are counted |
The emulation bet
NVIDIA's answer to shrinking FP64 hardware is FP64 emulation. Since CUDA 13.0 Update 2 (October 2025), cuBLAS can compute FP64 matrix multiplies on INT8 tensor cores using the Ozaki scheme. NVIDIA claims "accuracy equal to or better than native FP64 matmul" with automatic precision selection, and "up to 13x" speedups on RTX PRO 6000. It names GB200 NVL72 and RTX PRO 6000 Blackwell Server Edition. NVIDIA Technical Blog
Emulation speeds up dense FP64 matrix multiplies (GEMM). A lot of HPC time is not GEMM: stencils, sparse solvers, FFTs, particle codes and reductions run on the vector FP64 units, which emulation doesn't touch. Also, B300 cut INT8 to 3 POPS, the very units the Ozaki scheme runs on, so emulation can't rescue B300. reasoned An HPC buyer should measure their own code, not the GEMM headline.
Which parts are HPC-centric, and why
- A100, H100/H200, B200/GB200, Rubin: high native FP64, HBM with ECC, NVLink and MIG. This is the set a national lab or weather service buys.
- GH200: the most HPC-shaped part, because the coherent CPU memory suits codes whose working set doesn't fit in HBM. NVIDIA positions it for "AI and HPC applications."
- Not HPC parts: B300/GB300 (FP64 gone), all RTX/L parts (low FP64, no NVLink), Rubin CPX (inference-only).
Part 6
The training and inference bets
NVIDIA's roadmap since 2024 reads as one large bet: inference, especially reasoning and agents, is the growth market, and it's best served by specialized hardware for each phase rather than one general GPU.
| Bet | Evidence | Source |
|---|---|---|
| Low precision for inference | FP4 (NVFP4) everywhere from Blackwell on. B300 trades FP64 and INT8 for 15 PF dense FP4. Rubin quotes 50 PF NVFP4 inference vs. 35 PF training | NVIDIA |
| Reasoning as the selling point | GB300 NVL72: "Designed for AI Reasoning Performance," for "test-time scaling inference" | NVIDIA GB300 page |
| Cost per token | Rubin: "up to 10x reduction in inference token cost"; for training, "4x reduction in number of GPUs to train MoE models" | NVIDIA newsroom, Jan 2026 |
| Disaggregated serving | NVIDIA's own framing: the context phase (prefill) is "compute-bound"; generation (decode) is "memory bandwidth-bound." "Compute-optimized GPUs accelerate prefill, while memory-optimized GPUs focus on decode," orchestrated by Dynamo | NVIDIA glossary |
| A prefill chip | Rubin CPX: 30 PF NVFP4 on 128 GB of cheap GDDR7, for "massive-context inference," promised for end of 2026. It is absent from NVIDIA's March 2026 Vera Rubin POD material. Trade press reports it was dropped; others report a redesign for Q1 2027. NVIDIA hasn't said | NVIDIA (announcement) status: trade press |
| A decode chip | Groq 3 LPX: a rack of 256 Groq 3 LPUs alongside Vera Rubin NVL72. LPX runs the latency-sensitive parts of decode (FFN and MoE experts); Rubin GPUs keep prefill and decode attention. NVL72 stays "the flexible, general-purpose workhorse for training and inference" | NVIDIA Technical Blog |
| Rack-scale training | NVL72 domains (GB200 → Vera Rubin) and Rubin Ultra NVL576 (8 racks in one NVLink domain, H2 2027). Training stays on the big general GPU | NVIDIA |
Training keeps the biggest general GPU and the largest NVLink domain. Inference gets split by phase: compute-heavy prefill on cheaper-memory parts (CPX, if it ships), latency-critical decode on SRAM-heavy parts (LPX), and Rubin in the middle. FP64 HPC is now a side customer served by emulation plus Rubin's restored native FP64. For anyone buying, the result is that "which GPU" is becoming "which mix of racks". reasoned
Part 7
What this means for a GPU service
Reasoned implications for anyone building a GPU service from mixed sites, not a recommendation for any specific deployment. reasoned
| Customer need | Fits | Avoid |
|---|---|---|
| Video transcoding, video AI, edge inference in air-cooled sites | L4 (72 W, NVENC), L40S | H100/H200 (no NVENC) |
| Single-GPU inference of models up to ~70B-class quantized, virtual workstations | RTX PRO 6000 Server (96 GB, MIG up to 4), L40S (vGPU) | GeForce (licence) |
| Hard multi-tenant slices with guarantees | H100/H200/B200 (MIG 7) with a DPU | L40S (no MIG) |
| Large-model serving and reasoning at scale | GB300 NVL72 now, Vera Rubin as it ramps | PCIe-only parts for tensor-parallel serving |
| FP64 science and engineering (HPC) | H200, B200, GH200, Rubin | B300/GB300, RTX/L |
| Frontier training | NVL72 racks, Rubin | Anything without NVLink |
Two procurement questions follow. First, can the site cool it? Liquid cooling decides whether GB/VR racks are even an option. Second, does anyone need FP64? If so, "newest" (B300) is the wrong answer.
Part 8
Open questions
- Does Rubin CPX ship, as GDDR7 or redesigned with HBM4? NVIDIA hasn't said since dropping it from its March 2026 material.
- MIG counts for B200, GH200 and Rubin, and Rubin's power per GPU. Not on the pages checked.
- What the ISC release counts as "a single rack" with "up to 144 GPUs", when the NVL72 product page lists 72 GPUs and 2,400 TF of FP64.
- The exact FP64 rate on RTX/L parts (commonly cited as 1/64 of FP32; not on NVIDIA's pages).
- How much real HPC code gets the Ozaki-scheme speedup, versus only GEMM benchmarks.
- When Vera Rubin capacity is actually rentable at neoclouds (partners named in NVIDIA's Q2 FY27 release include CoreWeave, Google Cloud, Azure, OCI and Nebius).